Roadmap 0.9, Hardware design: HDL to silicon (Track HD)
HD.3 Chip design: Liberty, LEF, DEF and SDC files
Our own readers and writers for cell timing and power libraries, floorplans and timing constraints, written from the public format descriptions.
Plan docs/0.8-PART8.md.
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Add detail as we go: how you would use it, files or steps that show the problem, what other programs do. The team reads every comment.
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